Some electronics applications require translation of a differential voltage to a ground referenced voltage. The trend in the electronics industry is to reduce the size and power consumption of electronic devices. In general, as device sizes decrease (e.g., sub micron technology devices), the effect of parasitic or stray capacitances and currents in the device become more problematic. Sub micron differential-to-ground referenced voltage translation circuits are no exception. In this type of circuit, parasitic capacitances can lead to significant voltage level inaccuracies in the translation process. In some conventional circuits, these inaccuracies can exceed the relatively strict tolerances required in many current electronic applications. Therefore, there is a need for differential-to-ground referenced voltage translation circuit with reduced susceptibility to inaccuracies caused by parasitics.
In accordance with the present invention, a translation circuit for transferring a differential voltage to a ground referenced voltage using a sample/hold capacitor is provided. The translation circuit is configured to sample and hold a differential voltage signal, and then translate the differential voltage signal sample into a ground-referenced voltage signal. In one aspect of the invention, the translation circuit includes a differential input circuit, a sample/hold (S/H) circuit, and a compensation circuit. The S/H circuit includes a S/H capacitor, a series capacitor and a switch. The S/H and series capacitors are connected in series between an output line and a source of ground potential (GROUND). The switch shorts the bottom electrode of the S/H capacitor to GROUND when executing a translation operation. The differential input circuit receives the differential voltage signal and selectively provides the differential voltage across the S/H capacitor so that the top and bottom electrodes of the S/H capacitor have voltages V+ and Vxe2x88x92, respectively. Parasitic capacitance tends to add charge to the S/H capacitor during the translation operation. The compensation circuit compensates for parasitic capacitance by removing, ideally, the same amount of charge from the S/H capacitor by the end of the translation operation.
In further aspect of the invention, the differential input circuit includes two switches (i.e. first and second switches) to selectively isolate the S/H circuit from the differential signal lines. The compensation circuit includes two switches (i.e., third and fourth switches) and a trim capacitor. The trim capacitor is connected in parallel with the S/H capacitor through the two switches of the compensation circuit. A timing circuit is configured to provide control signals to operate the switches.
In operation, the S/H and trim capacitors are charged to the differential voltage and then isolated from the differential voltage lines by opening the first and second switches. The third switch then connects bottom electrode of the trim capacitor to GROUND. Consequently, the voltage at the bottom electrode of the trim capacitor is pulled from Vxe2x88x92 to 0 volts, causing charge to flow from the S/H capacitor to the trim capacitor. A relatively small amount of charge also flows from the parasitic capacitance. Then the fourth switch is opened to isolate the trim capacitor from the S/H capacitor. The switch of the S/H circuit (i.e., the fifth switch) is then closed to short the series capacitor and connect the bottom electrode of the S/H capacitor to GROUND. Consequently, the voltage at the bottom electrode of the S/H capacitor is pulled from Vxe2x88x92 to 0 volts, causing charge to flow from the parasitic capacitance to the S/H capacitor.
In accordance with this aspect of the invention, the trim capacitor is sized to compensate for the parasitic capacitances in the translation circuit. The trim capacitor is sized to have approximately the same capacitance value as that of the parasitic capacitance so that the amount of charge that flows from the parasitic capacitance when pulling the voltage of the bottom electrode of the S/H capacitor from Vxe2x88x92 to 0 volts will be the same as the amount of charge that flows from the trim capacitor when pulling the voltage at the bottom electrode of the trim capacitor from Vxe2x88x92 to 0 volts.